The invention relates to the field of connection of data transmission medium to integrated circuit packages.
Increasing the integration density in planar integrated circuits (ICs) leads to a reduction of feature sizes and denser packing of devices. While transistor switching speed benefits from this evolution, the delay time due to on-chip wiring increases markedly and limits along with inter-chip wiring the overall performance of ICs and systems.
3D packaging methods are known (e.g., package-on-package (PoP)) which account for space savings by stacking separate chips into a single package. With such methods, however, chips have to communicate via off-chip signaling. In contrast, a true vertically integrated chip stack is composed of multiple dies wherein die components communicate with on-chip signaling, horizontally and with through-silicon-vias vertically. Thus, 3D integration of ICs significantly reduces the wiring length by providing vertical pathways for signal (and power) transmission. 3D integration allows large numbers of vertical vias between the layers. This allows for construction of wide bandwidth buses between functional blocks in different layers with comparably low power consumption. A typical example is a processor+memory 3D stack, with the cache memory stacked on top of the processor. Such an arrangement provides massive bandwidth improvement, see e.g., “Predicting the Performance of a 3D Processor-Memory Chip Stack” Jacob, P. et al. Design & Test of Computers, IEEE Volume 22, Issue 6, November-December 2005 Page(s): 540-547. In addition, the stacking approach is highly modular and enables the integration of dissimilar technologies in a single cube.
To exploit the full potential of today and future high-performance CPUs (stacks), the total input/output (hereafter IO) bandwidth may have to scale to more than 10 Terabits per second (Tbps) per chip (stack). At the same time the number of off-chip electrical connections (e.g. solder balls) available per die is only slowly increasing. Accordingly, power and signal delivery to single IC dies is already constrained. The number of electrical connections at the stack bottom is invariant with the stacking of high performance IC dies, hence the number of connections used for power delivery is increasing and constraining the signal connections even further.